GPS disciplined OCXO project

VK2RK

Active member
Moving on into the next design, a GPS disciplined OCXO using a UBLOX GPS module along with a bunch of ripple counters and a PLL chip
The frequency divider part could be used as a standalone device to provide 10, 5, 1 MHz with just one 74HC390, using two will provide a 10KHz signal to compare with the 10KHz from the GPS module and provide a phase lock, at least in theory.. Stay tuned as I go down this rabbit hole.

GPS-OCXO.jpg
GPS .jpg
 

Josh

New member
I remember seeing a rather inspired design that used a the 10Mhz through a by ten divider into the reset input of a HC4046 and i think the GPS 1PPS output was feed into the set, the result was a pulse which duration was the phase of the PPS relative to the 1MHz clock. The HC4046 output was feed into a external charge hold circuit for an microcontroller adc. I though that was a really clever way to get the phase drift information to a high degree at a high rate. Maybe you can use the idea.
 

VK2RK

Active member
I remember seeing a rather inspired design that used a the 10Mhz through a by ten divider into the reset input of a HC4046 and i think the GPS 1PPS output was feed into the set, the result was a pulse which duration was the phase of the PPS relative to the 1MHz clock. The HC4046 output was feed into a external charge hold circuit for an microcontroller adc. I though that was a really clever way to get the phase drift information to a high degree at a high rate. Maybe you can use the idea.
Been thinking on similar lines, hence the choice of phase comparator that include the two D type flipflops and not just exclusive OR's
The Jitter from the GPS module that is a function of both the internal divider based on a 38KHz internal clock and Satellite timing differences I estimate to be in the range of 400 pS to a worst case occasional of 5nS, I don't have any equipment to more accurately measure the jitter or evaluate in more detail, thus by making some assumptions and using integration technique that I can apply in the Low pass filter to the OCXO control voltage, so here I can average out any jitter causing no correction to the control voltage only that of actual frequency drift. At least that is the plan. Also note that now I can select either 100 or 10 KHz as a reference, this to test my assumption, if the integration averaging works I should be able to increase the reference frequency. Time will tell.

All the design so far has been theoretical, the board has been ordered along with the IC's, I did hope to test my theory on a PLL chip but I cant get one locally, all answers will be found on the prototype, hopefully emerge from the rabbit hole.

I am attaching the final drawing and PCB
GPS-OCXO_PCB.jpg
GPS-OCXO.jpg
 
Last edited:
Top